3 ms·
x86 has encodings for shifts by 1 that are two bytes, so there's no code size advantage.
by gsg 14y ago
x86 has encodings for shifts by 1 that are two bytes, so there's no code size advantage.
- mpyne 14y agoSometimes there are "canonical forms" for these operations depending on what chip is being targeted, where the hardware can automatically break data dependencies and improve hardware-level parallelism, as long as the instruction is encoded in the right form. I don't know that this is necessarily the reason here, but it's one possible explanation.