You could save attempt to use some kind of parallel setup down to the silicon layer to achieve these data throughputs. [S R ][bit0]->[line 0] [H E ][bit1]-

You could save attempt to use some kind of parallel setup down to the silicon layer to achieve these data throughputs. [S R ][bit0]->[line 0] [H E ][bit1]->[line 1] [I G ][bit2]->[line 2] [F I ][bit3]->[line 3] [T STER...etc. It's late over here though, so I expect this design to have an obvious fatal flaw.