4 ms·

Well, assuming a current cpu core is ~30mm square, you would need to shrink the feature size by two orders of magnitude... so current 45nm features would need t

Well, assuming a current cpu core is ~30mm square, you would need to shrink the feature size by two orders of magnitude... so current 45nm features would need to shrink to ~500 picometers. According to wikipedia, a 'standard atom' is between 60 and 600 picometers in diameter, so yeah, you'd need transistors the size of atoms. Of course, this is assuming the same general processor design. You could go 3D and get everything closer together without shrinking transistors as much... or you could change the design all together.

Retric 18y ago
That's one option the other is using a longer pipeline. However, the cache does not need to operate at that speed only the core so it's best to ignore the cache, but I can't find good numbers on a naked CPU. Anyway, using a 55nm GPU 285 GTX that has a 470 mm die size and 240 processor elements we can see each element is only using ~2mm of die. Which is only off by a factor of 4 so ~14nm would work. In theory you could end up with a ~1THz GPU with ~1000 SPs and around 4000x more processing power. But it would need insane memory bandwidth etc.
- yan 18y ago
  What about heat? Area that small operating that fast would generate an intense amount of heat.
  - Xichekolas 18y ago
    In another only-slightly-related article (about Graphene Memory developed at Rice), they note that graphene based trasistors require 1/1,000,000th the switching power (because they leak less), and operate successfully from -75C to 200C, so it might not be an issue. But really this is totally speculation until someone builds one. Link to article about Graphene Memory: http://www.dailytech.com/Researchers+Create+New+Memory+from+Graphene/article13737.htm http://www.dailytech.com/Researchers+Create+New+Memory+from+...
- ComputerGuru 18y ago
  Longer pipelines proved to be pretty much a dead end with the Pentium 4. They're great and all when it comes to benchmarks and stuff, but their design has a number of serious drawbacks: 1) The control lines for a long pipeline are incredibly convoluted/complicated as necessitated by the movement of individual instructions from one stage to the other along the pipeline across many, many cycles (all of which involve storing the results of the current cycle to a register somewhere along the pipeline, adding immense overhead in today's systems). 2) Flushing longer pipelines is an incredibly taxing procedure. You either flush the entire pipeline and lose a huge chunk of work, basically throwing out several thousand cycles of work as a result of a single branch or value mis-prediction; or you can selectively clear the pipeline which is an extraordinarily difficult feat that involves keeping track of which operation in what order wrote back what data to which register... for dozens of operations.
  - Retric 18y ago
    All modern PC CPU's have a pipeline. Granted long pipelines suck, but my point was you can have a higher clock speed than the time it takes light to travel from one end of you're CPU to the other and back. One of the more interesting options IMO is to have 2 separate threads with separate registers using the same hardware so you can interleave calculations without a long pipeline. The issue becomes do you have 2 half speed virtual cores or a single high clock speed core and what do you do about instructions that take more than one clock cycle.
    - ComputerGuru 18y ago
      Oh, I'm not denying the merits of pipelining - no one can. I'm just saying that nothing is good when taken to the extreme. The "more interesting option" you're referring to is implemented in P4 and Nehalem under the trademark of "HyperThreading."
      - scott_s 18y ago
        The non-marketing name is Simultaneous Multithreading (SMT), but I've never been impressed with SMT performance. I think the emerging processors that use many simpler cores will have more impact.
anamax 18y ago
You're assuming that chip sizes are bounded by clock frequency. They're not. We already have "clock islands".

Retric 18y ago

That's one option the other is using a longer pipeline. However, the cache does not need to operate at that speed only the core so it's best to ignore the cache, but I can't find good numbers on a naked CPU. Anyway, using a 55nm GPU 285 GTX that has a 470 mm die size and 240 processor elements we can see each element is only using ~2mm of die. Which is only off by a factor of 4 so ~14nm would work. In theory you could end up with a ~1THz GPU with ~1000 SPs and around 4000x more processing power. But it would need insane memory bandwidth etc.

yan 18y ago
What about heat? Area that small operating that fast would generate an intense amount of heat.
- Xichekolas 18y ago
  In another only-slightly-related article (about Graphene Memory developed at Rice), they note that graphene based trasistors require 1/1,000,000th the switching power (because they leak less), and operate successfully from -75C to 200C, so it might not be an issue. But really this is totally speculation until someone builds one. Link to article about Graphene Memory: http://www.dailytech.com/Researchers+Create+New+Memory+from+Graphene/article13737.htm http://www.dailytech.com/Researchers+Create+New+Memory+from+...
ComputerGuru 18y ago
Longer pipelines proved to be pretty much a dead end with the Pentium 4. They're great and all when it comes to benchmarks and stuff, but their design has a number of serious drawbacks: 1) The control lines for a long pipeline are incredibly convoluted/complicated as necessitated by the movement of individual instructions from one stage to the other along the pipeline across many, many cycles (all of which involve storing the results of the current cycle to a register somewhere along the pipeline, adding immense overhead in today's systems). 2) Flushing longer pipelines is an incredibly taxing procedure. You either flush the entire pipeline and lose a huge chunk of work, basically throwing out several thousand cycles of work as a result of a single branch or value mis-prediction; or you can selectively clear the pipeline which is an extraordinarily difficult feat that involves keeping track of which operation in what order wrote back what data to which register... for dozens of operations.
- Retric 18y ago
  All modern PC CPU's have a pipeline. Granted long pipelines suck, but my point was you can have a higher clock speed than the time it takes light to travel from one end of you're CPU to the other and back. One of the more interesting options IMO is to have 2 separate threads with separate registers using the same hardware so you can interleave calculations without a long pipeline. The issue becomes do you have 2 half speed virtual cores or a single high clock speed core and what do you do about instructions that take more than one clock cycle.
  - ComputerGuru 18y ago
    Oh, I'm not denying the merits of pipelining - no one can. I'm just saying that nothing is good when taken to the extreme. The "more interesting option" you're referring to is implemented in P4 and Nehalem under the trademark of "HyperThreading."
    - scott_s 18y ago
      The non-marketing name is Simultaneous Multithreading (SMT), but I've never been impressed with SMT performance. I think the emerging processors that use many simpler cores will have more impact.

anamax 18y ago

You're assuming that chip sizes are bounded by clock frequency. They're not. We already have "clock islands".