I guess it's because I have mainly seen FPGAs in time-critical situations (where CPUs can't be used) in which it was very difficult to predict their performance

I guess it's because I have mainly seen FPGAs in time-critical situations (where CPUs can't be used) in which it was very difficult to predict their performance and they required lots of hand-tweaking I suspect that if you used FPGAs for less time critical applications, you'd have more room for productivity tradeoffs. Inside FPGAs though, the timing is not as uniformly discretized. It's about taking resources of routing distance from a large pool with a large geographical component, making it highly non-linear and tricky to predict. Such details can be abstracted over. If you only create synchronous circuits, for example, these subtle timing considerations can be handled automatically. W/r/t additional hardware, I meant hardware that configures the bitstream, such as a header or CPU interface, as well as power supplies. I don't really understand why such additional hardware is necessary, I'm not able to comment.