The argument could be made that this is due to the "high level" nature of x86 assembly :-). On the actual physical chip such an instruction does involve interm

The argument could be made that this is due to the "high level" nature of x86 assembly :-). On the actual physical chip such an instruction does involve intermediate register-like storage, and this storage exists by necessity: After all, on the electrical level, the operation is carried out by waiting for the voltage levels on some output "wires" to stabilize while the intermediate network of transistors is presented the input voltages continually. In this case, that would take 1 clock tick - after which the probability that the output pattern represents XOR is almost 1 (there is a neglible chance of failure). The point is: we cannot predict such circuits precisely enough when the output really is directly connected to the input (that would be a resonating feedback loop, after all - and we only know the input voltage to within some tolerance, not to mention quantummechanical effects), so there's always some gating and that means some intermediate storage. Even when the instruction set hides that from you.