You don't need 4 times the memory pipelines. If you have one pipeline and cores issue few enough requests for bandwidth to not be a problem, then contentions be

You don't need 4 times the memory pipelines. If you have one pipeline and cores issue few enough requests for bandwidth to not be a problem, then contentions between cores only cost you 0-3 cycles of latency, which is a tiny cost compared to DRAM latency these days. A more relevant factor is how many banks the DRAM has compared to how many cores are issuing bank-missing requests in parallel.