4 ms·
This isn't correct because in either case you're almost certainly sharing the same memory controller, which still has to service requests one at a time (if they
by iyulaev 14y ago
This isn't correct because in either case you're almost certainly sharing the same memory controller, which still has to service requests one at a time (if they are randomly dispersed in memory). Furthermore if the memory access takes long enough the single-core can context switch to another process and run non-blocked instructions there. The 4-core version doesn't magically have 4 times the memory pipelines, and the 1-core version won't stupidly sit waiting for a memory access to return.
- _yosefk 14y agoYou don't need 4 times the memory pipelines. If you have one pipeline and cores issue few enough requests for bandwidth to not be a problem, then contentions between cores only cost you 0-3 cycles of latency, which is a tiny cost compared to DRAM latency these days. A more relevant factor is how many banks the DRAM has compared to how many cores are issuing bank-missing requests in parallel.