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We are testing [0] our Sparc v8 compiler backend. Apparently, a 3GHz i7 core emulating Sparc is significantly faster than an FPGA synthesized Sparc. [0] http:/
by qznc 14y ago
We are testing [0] our Sparc v8 compiler backend. Apparently, a 3GHz i7 core emulating Sparc is significantly faster than an FPGA synthesized Sparc.
[0] http://pp.info.uni-karlsruhe.de/git/firm-testsuite/ http://pp.info.uni-karlsruhe.de/git/firm-testsuite/
- jws 14y agoSchedule change. Today's project is to see is qemu running a big endian PPC delivers acceptable performance for testing software in a bigendian environment. I could retire an old Mac Mini PPC running Debian.
- justincormack 14y agoGood idea might try that too...
- dorianj 14y agoWhat kind of FPGA package were you previously using? Many FPGA CPU simulators attempt to be cycle-accurate for the purpose of architecture development, where the emulator has the leeway of treating instructions as atomic units and abstracting the rest.
- qznc 14y agoWould have to ask my colleague about the details, but yes it is cycle-accurate. It is running 50 or 80 MHz, so it is expected to run slower.