Pardon me, I'm not a CPU architect but I have a couple of questions. Why would prefetch and decode affect out of order execution? Prefetch and decode is done

Pardon me, I'm not a CPU architect but I have a couple of questions. Why would prefetch and decode affect out of order execution? Prefetch and decode is done on the frontend of the chip, so you'll have prefetch happening on L3, L2 and L1, along with decode and u-op breakdown. This is a matter of memory throughput getting instructions from the bus into the caches. The out-of-order execution should be a matter of issuing to the backend execution units. It is true that the backend will be stalled if we don't issue quickly, but that's where you have staging and prefetch on the front end side. At least the above is what I thought to be the case. I could be very wrong. Please educate if I've gotten something wrong. Also we do have the matter of throughput vs completion of an instruction, basically a tradeoff. Deeper pipelines so can have more throughput but take the hit of longer completion times. Again might be bad for certain tasks, but going through more sillicon isn't necessarily always bad. Thanks.