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Your post and the link to KiCadRoutingTools is going to result in me finishing a project I started 6 months ago and have just let sit and linger because, like y

Your post and the link to KiCadRoutingTools is going to result in me finishing a project I started 6 months ago and have just let sit and linger because, like you point out, it was only the boring parts left. Fable found a bit of a showstopper in my design yesterday (an LDO that was right near its limits) and suggested a replacement, Opus filled in all of the missing pull-up/pull-down resistor values, double-checked all of the decoupling caps, and then did floor planning on the PCB side. I just installed KiCadRoutingTools and am getting close to happy with the state of the board and will likely be ordering them tomorrow!

a6mzero 9d ago
Great to hear :) I hope your boards will turn out perfectly fine.
- tonyarkles 7d ago
  As a quick WIP update: - The first board, which I had already done manual schematic capture, floor planning, and some routing on (but then I lost steam and it’s been sitting at 90% for 6 months) was finished quite readily by Opus + KiCadRoutingTools. - A second significantly more complex board that has been sitting at the “I’ve done a bunch of planning in Obsidian but haven’t started schematic capture yet” stage… Fable took my Markdown notes, asked questions to fill in the blanks, and put together a plan. Opus first put together a very ugly schematic (essentially all of the parts but no wires between them, just net connections) which then got refined into a nicer-ish schematic. Floor planning went smoothly, the first cut was decent and with a little bit of manual refinement it got somewhere pretty good. Currently routing and still debating a bit between 4-layer and 6-layer. The BGA escapes seem to be causing the majority of the problems right now; originally Opus decided that 4-layer wasn’t feasible due to not being able to even route all the nets, switched to 6-layer, did better but still ended up with like 70 unroutable nets. A bit of back and forth led to revising the BGA fan-out and now we’re back at looking at whether a 4-layer board might be feasible. For the second one, I’m not 100% sure whether wall-clock-time this is a faster process than it would’ve been to do manually, but… the initial 4-layer attempts were all done while I was out for a date with my wife, the remaining 4-layer attempts ran overnight, the first 6-layer routing attempt was done while I was having my coffee this morning, and now the 4-layer/6-layer fanout changes are being done while I run errands. Something I find especially interesting is that by leaning on KiCadRoutingTools, it looks like there’s actually very little token usage at the routing stage; the plan gets put together as Python + KiCadRoutingTools instructions and then the hard work is done by that tooling. LLM picks up the results, looks at it, tweaks, kicks off a new job. That’s a pretty interesting result; this has all been running on my laptop pretty much continuously for 15 hours and I’m nowhere near any of my usage limits.

a6mzero 9d ago

Great to hear :) I hope your boards will turn out perfectly fine.

tonyarkles 7d ago
As a quick WIP update: - The first board, which I had already done manual schematic capture, floor planning, and some routing on (but then I lost steam and it’s been sitting at 90% for 6 months) was finished quite readily by Opus + KiCadRoutingTools. - A second significantly more complex board that has been sitting at the “I’ve done a bunch of planning in Obsidian but haven’t started schematic capture yet” stage… Fable took my Markdown notes, asked questions to fill in the blanks, and put together a plan. Opus first put together a very ugly schematic (essentially all of the parts but no wires between them, just net connections) which then got refined into a nicer-ish schematic. Floor planning went smoothly, the first cut was decent and with a little bit of manual refinement it got somewhere pretty good. Currently routing and still debating a bit between 4-layer and 6-layer. The BGA escapes seem to be causing the majority of the problems right now; originally Opus decided that 4-layer wasn’t feasible due to not being able to even route all the nets, switched to 6-layer, did better but still ended up with like 70 unroutable nets. A bit of back and forth led to revising the BGA fan-out and now we’re back at looking at whether a 4-layer board might be feasible. For the second one, I’m not 100% sure whether wall-clock-time this is a faster process than it would’ve been to do manually, but… the initial 4-layer attempts were all done while I was out for a date with my wife, the remaining 4-layer attempts ran overnight, the first 6-layer routing attempt was done while I was having my coffee this morning, and now the 4-layer/6-layer fanout changes are being done while I run errands. Something I find especially interesting is that by leaning on KiCadRoutingTools, it looks like there’s actually very little token usage at the routing stage; the plan gets put together as Python + KiCadRoutingTools instructions and then the hard work is done by that tooling. LLM picks up the results, looks at it, tweaks, kicks off a new job. That’s a pretty interesting result; this has all been running on my laptop pretty much continuously for 15 hours and I’m nowhere near any of my usage limits.