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I've never actually done hardware design. I last looked at it a few years ago and it seemed really confusing. What I really want is an FPGA on a board like th
by csense 14y ago
I've never actually done hardware design. I last looked at it a few years ago and it seemed really confusing.
What I really want is an FPGA on a board like the Raspberry Pi, where I can just plug in USB, network and power, copy-paste some code from a tutorial, have it run, and start learning HDL from that point.
I want to be able to develop an FPGA program that can maybe do a specific bitwise computation faster than a CPU or GPU (like SHA hashes for bitcoin mining, but this is just one example) and send inputs and outputs back and forth with a regular computer. Without also having to design and solder my own circuit board in order to do it.
It seems, though, like as soon as you say the word "FPGA," people automatically assume you have a ton of experience and equipment for building your own circuit boards. Which I really don't. And learning this on the same project learning HDL seems like it would really make things kinda hard. "It doesn't work" could mean anything from a solder blob shorting two wires, to some screw-up earlier in the process having destroyed a component and now it'll never work even if you do the rest of it correctly (and you have to increase your budget to replace the now-fried chip), to a failure to understand something about HDL, to some electromagnetic bug in the design of the circuit (like "you need a capacitor here, you need an inductor there, your resistor is 100x too big or too small")...a bug in the HDL of course...or it could be a bug in the USB interface hardware/software I made on the board...or in the custom USB driver I wrote (I've also never actually written a hardware driver before) running on the general-purpose computer...In short, it seems like, to get started teaching yourself hardware design, you have to have approximately one university degree worth of hardware design knowledge already.
Learning HDL, I want to be able to eliminate all of the above sources of error but "if it doesn't work, it must be a bug in my HDL code."
Bootstrapping software programming through self-learning is easy enough that probably at least tens of thousands of middle and high school kids do it on their own every year (I was one of them). Bootstrapping GPU programming is a little harder but still seems doable (I haven't actually done more than dabbling, though). Bootstrapping FPGA should be just as easy, but it isn't.
I haven't been able to find what hardware I should buy to do this, and I haven't even been able to figure out what search terms I should be using. It's been a few years since I looked, though, so maybe I should look again.
- robomartin 14y agoHonestly, there's absolutely nothing that would prevent you from learning HDL. There are a number of excellent development boards and tutorials. Start here: http://www.xilinx.com/university/students/index.htm http://www.xilinx.com/university/students/index.htm The issue with doing higher-level work is that you really need to understand circuit design and implementation. A lot of what you do in an FPGA is to type out text that looks like code but in reality is a "secret contract" with the compiler for it to "infer" the circuit you want. In many ways you could say that there are idioms that you learn that will result in specific circuit constructs once they go through one turn of the wheel. Then there's the issue of optimization. Sometimes you just don't get the performance you want and have to resort to, effectively, hand-wiring stuff in code. Whether VHDL or Verilog, you have the ability to literally hand-wire FPGA internals to build circuits that usually perform or place better than the what the tools can do: (sorry, this is long) module ADDER #(parameter WIDTH = 8) ( input wire CLK, input wire CE, input wire RST, input wire CIN, input wire [WIDTH - 1:0] A, input wire [WIDTH - 1:0] B, output wire [WIDTH:0] SUM ); genvar i; wire [WIDTH - 1:0] xor2; wire [WIDTH:0] cy; wire [WIDTH - 1:0] xorcy; assign cy[0] = CIN; generate for(i=0; i <= WIDTH; i=i+1) begin:BIT if(i != WIDTH)begin:_ myXOR2 x(.O(xor2[i]), .I0(A[i]), .I1(B[i])); MUXCY m(.O(cy[i+1]), .CI(cy[i]), .DI(A[i]), .S(xor2[i])); XORCY xc(.O(xorcy[i]), .CI(cy[i]), .LI(xor2[i])); FDRE f(.Q(SUM[i]), .C(CLK), .CE(CE), .D(xorcy[i]), .R(RST)); end else begin:_ FDRE f(.Q(SUM[i]), .C(CLK), .CE(CE), .D(cy[i]), .R(RST)); end end endgenerate //synthesis attribute RLOC of BIT[0]._.x is X0Y0 //synthesis attribute RLOC of BIT[1]._.x is X0Y0 //synthesis attribute RLOC of BIT[2]._.x is X0Y1 //synthesis attribute RLOC of BIT[3]._.x is X0Y1 //synthesis attribute RLOC of BIT[4]._.x is X0Y2 //synthesis attribute RLOC of BIT[5]._.x is X0Y2 //synthesis attribute RLOC of BIT[6]._.x is X0Y3 //synthesis attribute RLOC of BIT[7]._.x is X0Y3 //synthesis attribute RLOC of BIT[8]._.x is X0Y4 //synthesis attribute RLOC of BIT[9]._.x is X0Y4 //synthesis attribute RLOC of BIT[10]._.x is X0Y5 //synthesis attribute RLOC of BIT[11]._.x is X0Y5 //synthesis attribute RLOC of BIT[12]._.x is X0Y6 //synthesis attribute RLOC of BIT[13]._.x is X0Y6 //synthesis attribute RLOC of BIT[14]._.x is X0Y7 //synthesis attribute RLOC of BIT[15]._.x is X0Y7 //synthesis attribute RLOC of BIT[16]._.x is X0Y8 //synthesis attribute RLOC of BIT[17]._.x is X0Y8 //synthesis attribute RLOC of BIT[18]._.x is X0Y9 //synthesis attribute RLOC of BIT[19]._.x is X0Y9 //synthesis attribute RLOC of BIT[20]._.x is X0Y10 //synthesis attribute RLOC of BIT[21]._.x is X0Y10 //synthesis attribute RLOC of BIT[22]._.x is X0Y11 //synthesis attribute RLOC of BIT[23]._.x is X0Y11 //synthesis attribute RLOC of BIT[24]._.x is X0Y12 //synthesis attribute RLOC of BIT[25]._.x is X0Y12 //synthesis attribute RLOC of BIT[26]._.x is X0Y13 //synthesis attribute RLOC of BIT[27]._.x is X0Y13 //synthesis attribute RLOC of BIT[28]._.x is X0Y14 //synthesis attribute RLOC of BIT[29]._.x is X0Y14 //synthesis attribute RLOC of BIT[30]._.x is X0Y15 //synthesis attribute RLOC of BIT[31]._.x is X0Y15 <... a bunch more of this snipped due to HN message length constraints ...> endmodule //synthesis attribute LUT_MAP of myXOR2 is YES; module myXOR2 ( output O, input I0, input I1 ); assign O = I0 ^ I1; endmodule That's the kind of thing you have to do if you have to squeeze the last MHz in performance out of an FPGA. That code was part of an FIR filter I designed that, about ten years ago, could not break 150MHz using the "hey compiler, you figure it out" approach. If I remember correctly, the hand-wired filter easily did 200MHz.