You are right, I wrote in an oversight that "Zero access latency" is practically possible within some margin. I was reading the book "The Cache Memory by Jim Ha

You are right, I wrote in an oversight that "Zero access latency" is practically possible within some margin. I was reading the book "The Cache Memory by Jim Handy" and on section 2.1.3 which says: "Occasionally, a designer will allow the CPU address to propagate through the address buffers to the bus at the beginning of every cycle, whether the cycle turns out to be a read hit or a read miss. The cache is designed in such a way as to initiate a main memory access at the same time as the cache access, rather than to wait for a cache miss before commencing the main memory access. This approach can shorten the main memory access time in the event of a cache miss and will serve to improve the operation of singleprocessor, single-tasking systems, but can work to the detriment of multitasking systems and multiprocessing systems, since the cache will allow the CPU to waste considerable amounts of main memory bus bandwidth. Such caches can be referred to as look aside designs. Since the processor has the option of going to either the cache or main memory at all times to request data, the look aside cache can be an add-on to the computer system." Because the book mainly focused on the older i386 processor memory design, I could have been clearer when describing common characteristics. I updated the common characteristics to include "Higher data-rate processing," which is relevant to the Prefetch architecture and its intent to support more data bits.