4 ms·

RISC-V Emulator and Linux System from Scratch

62 points by Bluestein 2mo ago

kvemkon 1mo ago
Discussion of the corresponding blog post: https://news.ycombinator.com/item?id=49553988 https://news.ycombinator.com/item?id=49553988
artemonster 1mo ago
// Load the Linux Kernel to the start of the RAM ram.write(0x00, LinuxKernel); lol
- gertop 1mo ago
  What's funny? That's how every linux computer start. The boot loader copies the kernel to RAM then jumps to it.
  - artemonster 1mo ago
    the obviousness and uselessness of the comment
peter_d_sherman 1mo ago
>"Source Code /lib contains the entire rv32ima instruction set emulator code as well as a minimal set of emulated devices" The author of this GitHub repository is not lying when he says "minimal" -- basically it's an emulated 8250 UART, and that's it! (Unless of course you count RAM (ram.hpp) and MMU (mmu.hpp) as "devices", in which case the emulated device count is three, as opposed to one...) Now, that's not a bad thing... in fact, that's a very very good thing, an excellent thing in fact! This whole project is brilliant! But, let's truly understand its brilliance. By writing this project the way it has been written, the author has stripped away somewhere between 1.5 to 2 million lines of QEMU source code (estimates put the lines of code in QEMU somewhere between these numbers), and replaced it with something far, far simpler to understand -- a decrease in the orders of magnitude of lines of code -- with a corresponding orders of magnitude increase of any given programmer's ability to understand the code. Phrased another way: "The learning curve for a programmer to understand a given piece of Open Source Software in a fixed time interval is approximately inversely proportional to its lines of code (LOC)." The above repository, by reducing the lines of code necessary for an emulator to run Linux to its absolute, barest, vanilla minimum, correspondingly allows students (and future students!) of emulators to get a foothold on understanding what's going on under the hood, while having to wrestle with the least amount of lines of code (or close to it!) necessary to gain this understanding. Well done! (And, a brilliant idea to only emulate a 8250 UART, by the way!)
- Bluestein 1mo ago
  I mean, this is as "from scratch" as I have ever seen a system built, really.-
Flex247A 1mo ago
Slight tangent: I made a similar but simpler project that runs DOOM on a custom RISC-V emulator: https://github.com/lalitshankarch/rvcore https://github.com/lalitshankarch/rvcore
westurner 1mo ago
Emulation of RISC-V in software; container2wasm has TinyEmu for RISC-V. dearchap/tinyemu: https://github.com/dearchap/tinyemu https://github.com/dearchap/tinyemu Qemu also supports 32bit and 64bit RISC-V: "RISC-V System emulator — QEMU documentation" https://www.qemu.org/docs/master/system/target-riscv.html https://www.qemu.org/docs/master/system/target-riscv.html Emu86 emulates RISC-V in Python and also WASM now IIRC: https://news.ycombinator.com/item?id=41899475 https://news.ycombinator.com/item?id=41899475 .. https://github.com/gcallah/Emu86/blob/master/assembler/virtual_machine.py#L643 https://github.com/gcallah/Emu86/blob/master/assembler/virtu... : class RISCVMachine(VirtualMachine): Also: (Box96/Box64 emulates x86 on ARM64 and RISC-V; e.g. Portal) From https://news.ycombinator.com/item?id=44979868 https://news.ycombinator.com/item?id=44979868 : > openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup https://github.com/openhwgroup

62 points by Bluestein 2mo ago

Discussion of the corresponding blog post: https://news.ycombinator.com/item?id=49553988 https://news.ycombinator.com/item?id=49553988

artemonster 1mo ago

// Load the Linux Kernel to the start of the RAM ram.write(0x00, LinuxKernel); lol

gertop 1mo ago
What's funny? That's how every linux computer start. The boot loader copies the kernel to RAM then jumps to it.
- artemonster 1mo ago
  the obviousness and uselessness of the comment

peter_d_sherman 1mo ago

>"Source Code /lib contains the entire rv32ima instruction set emulator code as well as a minimal set of emulated devices" The author of this GitHub repository is not lying when he says "minimal" -- basically it's an emulated 8250 UART, and that's it! (Unless of course you count RAM (ram.hpp) and MMU (mmu.hpp) as "devices", in which case the emulated device count is three, as opposed to one...) Now, that's not a bad thing... in fact, that's a very very good thing, an excellent thing in fact! This whole project is brilliant! But, let's truly understand its brilliance. By writing this project the way it has been written, the author has stripped away somewhere between 1.5 to 2 million lines of QEMU source code (estimates put the lines of code in QEMU somewhere between these numbers), and replaced it with something far, far simpler to understand -- a decrease in the orders of magnitude of lines of code -- with a corresponding orders of magnitude increase of any given programmer's ability to understand the code. Phrased another way: "The learning curve for a programmer to understand a given piece of Open Source Software in a fixed time interval is approximately inversely proportional to its lines of code (LOC)." The above repository, by reducing the lines of code necessary for an emulator to run Linux to its absolute, barest, vanilla minimum, correspondingly allows students (and future students!) of emulators to get a foothold on understanding what's going on under the hood, while having to wrestle with the least amount of lines of code (or close to it!) necessary to gain this understanding. Well done! (And, a brilliant idea to only emulate a 8250 UART, by the way!)

Bluestein 1mo ago
I mean, this is as "from scratch" as I have ever seen a system built, really.-

Flex247A 1mo ago

Slight tangent: I made a similar but simpler project that runs DOOM on a custom RISC-V emulator: https://github.com/lalitshankarch/rvcore https://github.com/lalitshankarch/rvcore

westurner 1mo ago

Emulation of RISC-V in software; container2wasm has TinyEmu for RISC-V. dearchap/tinyemu: https://github.com/dearchap/tinyemu https://github.com/dearchap/tinyemu Qemu also supports 32bit and 64bit RISC-V: "RISC-V System emulator — QEMU documentation" https://www.qemu.org/docs/master/system/target-riscv.html https://www.qemu.org/docs/master/system/target-riscv.html Emu86 emulates RISC-V in Python and also WASM now IIRC: https://news.ycombinator.com/item?id=41899475 https://news.ycombinator.com/item?id=41899475 .. https://github.com/gcallah/Emu86/blob/master/assembler/virtual_machine.py#L643 https://github.com/gcallah/Emu86/blob/master/assembler/virtu... : class RISCVMachine(VirtualMachine): Also: (Box96/Box64 emulates x86 on ARM64 and RISC-V; e.g. Portal) From https://news.ycombinator.com/item?id=44979868 https://news.ycombinator.com/item?id=44979868 : > openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup https://github.com/openhwgroup