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Yes, only one day of processing is impossible for any kind of integrated circuit. One day of processing would be possible only for semi-custom integrated circu

Yes, only one day of processing is impossible for any kind of integrated circuit. One day of processing would be possible only for semi-custom integrated circuits, like gate arrays, which have already been fabricated until a last step that only adds one or two custom metal layers to interconnect the existing components and then separates and packages the devices. Even with that, one day of processing would be possible only for making a small number of chips, where the metal layers would be patterned without masks, by direct exposure of the photoresist with a laser projector. Making photolithography masks would take more than one day.

gfdhjd3 1mo ago
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nfjesifb 19d ago
This is not unilaterally true if the devices are simple enough and make process engineering decisions specifically toward the objective of speed. I am not working on gate arrays and have made NMOS from a virgin p-type wafer in 8hrs. Some ways you can be fast: - Stock pre implanted wafers with oxide and polysilicon layers grown/deposited in advance to avoid any long furnace cycles at fabrication time. -Use spin on dopant with rapid thermal anneal furnaces instead of sending wafer to external services for implant whenever possible - Use SOI wafer and mesa isolation instead of more complicated and time intensive STI or LOCOS techniques - SOI also gives you the ability to do work function engineering that could allow for junctionless devices, further minimizing need for implant/doping steps because you don't need to form wells in oppositely doped bulk silicon - Instead of exclusively relying maskless lithography, which inherently means your exposures have to be done in sequence, you can instead rely on a combination of maskless and masked lithography so that as soon as you receive an order, you can start fabrication immediately by doing the first layer on a maskless setup while initiating mask writes for all subsequent layers in parallel across multiple mask writers. This parallelizes the lithography of every layer. I am happy to talk more specifically if there is any feedback or questions about these points. AMA.

gfdhjd3 1mo ago

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nfjesifb 19d ago

This is not unilaterally true if the devices are simple enough and make process engineering decisions specifically toward the objective of speed. I am not working on gate arrays and have made NMOS from a virgin p-type wafer in 8hrs. Some ways you can be fast: - Stock pre implanted wafers with oxide and polysilicon layers grown/deposited in advance to avoid any long furnace cycles at fabrication time. -Use spin on dopant with rapid thermal anneal furnaces instead of sending wafer to external services for implant whenever possible - Use SOI wafer and mesa isolation instead of more complicated and time intensive STI or LOCOS techniques - SOI also gives you the ability to do work function engineering that could allow for junctionless devices, further minimizing need for implant/doping steps because you don't need to form wells in oppositely doped bulk silicon - Instead of exclusively relying maskless lithography, which inherently means your exposures have to be done in sequence, you can instead rely on a combination of maskless and masked lithography so that as soon as you receive an order, you can start fabrication immediately by doing the first layer on a maskless setup while initiating mask writes for all subsequent layers in parallel across multiple mask writers. This parallelizes the lithography of every layer. I am happy to talk more specifically if there is any feedback or questions about these points. AMA.