> Unfortunately the amount of time it takes to get a feature like this into an Intel CPU is a bit mind boggling. I think this is an unfair feature comparison.

> Unfortunately the amount of time it takes to get a feature like this into an Intel CPU is a bit mind boggling. I think this is an unfair feature comparison. Zeroing L1 cache is way simpler operation than TM which has been designed to support two modes of operation [legacy -- which only speeds up traditional LOCK-based synchronization -- and true TM], must support transaction aborts and restarts, etc. Also, 10 years ago, TM was still a very active research area -- i.e., people had no clue about which ideas were performant and scalable and, not the least, feasible to implement in HW.