Missing from this post is any sort of discussion about how modern x86 CPUs are poorly designed for the types of programs most people are developing these days.

Missing from this post is any sort of discussion about how modern x86 CPUs are poorly designed for the types of programs most people are developing these days. Managed language runtimes represent the bulk of programs people are running on servers (think: Java/Scala/Clojure, PHP, Python, Ruby). These environments not only lack "mechanical sympathy" but also have requirements above and beyond what x86 can do. To take Cliff Click's word for it, managed language runtimes consume 1/3 of their memory bandwidth on average zeroing out memory before handing objects to people. If x86 supported an instruction for doing just-in-time zeroing into L1 cache, this penalty could be eliminated, and that 1/3rd of memory bandwidth could be used for actual memory accesses instead of just zeroing out newly allocated objects. In an age where RAM is the new disk, this would be huge. Unfortunately the amount of time it takes to get a feature like this into an Intel CPU is a bit mind boggling. Azul started talking to Intel about hardware transactional memory early last decade, and Intel is finally shipping hardware transactional memory in the Haswell architecture in the form of transactional synchronization extensions.