You can normalise by surface area, which makes defects rate comparable across processes. At least to a first order approximation, keeping all other parameters c

You can normalise by surface area, which makes defects rate comparable across processes. At least to a first order approximation, keeping all other parameters constant, bigger chips are more likely to have a defect because they have larger surface areas. If a process has a defect rate of x, the probability of a die having a defect is A*x. The limit is then the defect rate for a die with the surface area of a transistor, you cannot really get any better than this. But that’s not very useful if you want to extrapolate what the defect rate would be on an improved or cheaper process.