> unless they figure out a way to keep it analog all the way (really cool but unlikely) Very unlikely for the connection to the cache RAM, seemingly impossible

> unless they figure out a way to keep it analog all the way (really cool but unlikely) Very unlikely for the connection to the cache RAM, seemingly impossible if we want to get an articulate output :) > they do claim to have a “Mead” design [1] designed to run GPT-3 [ - i.e. to hold a 175b NN - ] in a single chip Careful: that is the /intention/, but the chip is just the storage (and CiM) for the NN and other parts are missing - explained in the Vanguard, not explained in the Mead. > Whether it works out or not will sadly be a matter of economics more than physics I fear Yes, but: -- what is not enabled today may often be tomorrow through advances, esp. in the economy of production; -- a very great point about this product seems to be that the chips can be rewritten, the NN is not etched and static (cpr. Taalas): that makes the practical implications extremely relevant, the demand would be "screaming mob" like; -- we have to go in that direction (of NNs in CiM) anyway, so it's just a matter of time, effort after effort we will get there.