3 ms·
In Taalas HC2 a chip embeds 20b parameters, and the declared idea is linking the chips. A card with two of them chips and you can already have a dense Qwen at s
by mdp2021 2mo ago
In Taalas HC2 a chip embeds 20b parameters, and the declared idea is linking the chips. A card with two of them chips and you can already have a dense Qwen at staggering speeds.
- x-complexity 2mo agoChiplet-style layouts could cut the etching quality requirements per chip down, but it still can't avoid the base cost for manufacturing silicon.
- mdp2021 2mo ago> it still can't avoid the base cost for manufacturing silicon What costs are you talking about and why would them be a problem? If it is the price: «Kharya says it costs 100x as much to train a model then to get a customize HC chip in reasonable volumes from Taalas» ( https://www.nextplatform.com/compute/2026/02/19/taalas-etches-ai-models-onto-transistors-to-rocket-boost-inference/4092140 https://www.nextplatform.com/compute/2026/02/19/taalas-etche... ). That is thinking about an LLM (logical) producer and server. For mass production, the costs go down. And in the case of a ~100b model as the poster mentioned, they would be just single PCI cards with 5 or 6 HC2 chips: doable and practical. I see more potential problems in the positioning of the SRAM - but not a real problem given that excellent team. To get a proper idea of the costs the architecture of the HC2 will have to be clearer.