You’re basically proving my point. As I said, it’s similar but incompatible, requiring a recompile or reassemble. The point being that the 32-bit instructions a

You’re basically proving my point. As I said, it’s similar but incompatible, requiring a recompile or reassemble. The point being that the 32-bit instructions are not a distinct subset of all the instructions with the 64-bit instructions added on. Some of the instruction encodings from rv32 are redefined in rv64 to operate on the larger register sizes. Rv64, for instance redefines the encoding for rv32 add to work on 64-bit registers and creates a new instruction to operate on 32-bit registers. Why didn’t they just extend rv32 to add a new “add 64-bit” instruction. If rv32 was a proper subset of rv64 then it would be easier. So, can you create a cpu that runs both? Sure, but you’ll need a mode and duplicate decoders, in whole or in part. Again not the end of the world (decoders are small these days) but it still makes you go wtf? Maybe there’s something I’m missing that offsets this complexity in some other way, but it’s not obvious what that is. It would have been better, imo, if rv64 (and rv128) was a set of newly added instructions with a cpuid or capabilities bit somewhere to let software know about the hardware capabilities, similar to SIMD instructions in x86. And yes, I realize that this is still less complex than x86, but that’s a low bar.