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> RISC-V doesn’t even support running 32-bit code on 64-bit processors without a recompile. In a sense, 32-bit RISC-V is a vaguely similar but incompatible ISA

> RISC-V doesn’t even support running 32-bit code on 64-bit processors without a recompile. In a sense, 32-bit RISC-V is a vaguely similar but incompatible ISA to 64-bit RISC-V RV32 and RV64 are considered distinct ISAs. But designed to divert as little as practical. Apart from the register size, differences are small enough to be (almost!) irrelevant. If you know RV32I assembly, then you know RV64I assembly & vice versa. Moving code between those is at worst a re-assemble away. Also it should be easy to support execution of RV32 binaries in userspace on a RV64 cpu (if some implementations supporting that don't exist already). AIUI, profiles were meant to provide a common target for eg. Linux distributions. Cases where you want 1 "generic" binary to support a variety of hardware like phone/tablet/SBC/desktop. Since these target the common case, yes profiles can be expected to grow & accumulate legacy cruft over time just like other ISAs. But for embedded or high-performance computing (HPC), this doesn't matter as code will be compiled for the specific hardware anyway. RISC-V's modular ISA is a great asset there. In the meanwhile: loootts of legacy cruft dumped (esp. compared to the insane x86 world). That's always welcome. Nothing's fixed in stone (not even silicon, imho), and tech should learn from past mistakes, improve things & move forward.

drob518 2mo ago
You’re basically proving my point. As I said, it’s similar but incompatible, requiring a recompile or reassemble. The point being that the 32-bit instructions are not a distinct subset of all the instructions with the 64-bit instructions added on. Some of the instruction encodings from rv32 are redefined in rv64 to operate on the larger register sizes. Rv64, for instance redefines the encoding for rv32 add to work on 64-bit registers and creates a new instruction to operate on 32-bit registers. Why didn’t they just extend rv32 to add a new “add 64-bit” instruction. If rv32 was a proper subset of rv64 then it would be easier. So, can you create a cpu that runs both? Sure, but you’ll need a mode and duplicate decoders, in whole or in part. Again not the end of the world (decoders are small these days) but it still makes you go wtf? Maybe there’s something I’m missing that offsets this complexity in some other way, but it’s not obvious what that is. It would have been better, imo, if rv64 (and rv128) was a set of newly added instructions with a cpuid or capabilities bit somewhere to let software know about the hardware capabilities, similar to SIMD instructions in x86. And yes, I realize that this is still less complex than x86, but that’s a low bar.

drob518 2mo ago

You’re basically proving my point. As I said, it’s similar but incompatible, requiring a recompile or reassemble. The point being that the 32-bit instructions are not a distinct subset of all the instructions with the 64-bit instructions added on. Some of the instruction encodings from rv32 are redefined in rv64 to operate on the larger register sizes. Rv64, for instance redefines the encoding for rv32 add to work on 64-bit registers and creates a new instruction to operate on 32-bit registers. Why didn’t they just extend rv32 to add a new “add 64-bit” instruction. If rv32 was a proper subset of rv64 then it would be easier. So, can you create a cpu that runs both? Sure, but you’ll need a mode and duplicate decoders, in whole or in part. Again not the end of the world (decoders are small these days) but it still makes you go wtf? Maybe there’s something I’m missing that offsets this complexity in some other way, but it’s not obvious what that is. It would have been better, imo, if rv64 (and rv128) was a set of newly added instructions with a cpuid or capabilities bit somewhere to let software know about the hardware capabilities, similar to SIMD instructions in x86. And yes, I realize that this is still less complex than x86, but that’s a low bar.