I disagree with some points in "RISC-V They Should Have Known Better". For example, author claims that saving and restoring all registers in interrupt handler

I disagree with some points in "RISC-V They Should Have Known Better". For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM is better because it has a "store multiple registers" instruction. It wouldn't help because storing multiple registers still requires multiple bus cycles, and microcontroller probably has a 32-bit bus and no cache, so saving N registers requires N memory cycles - no matter, is it done with a single instruction (ARM), or with multiple (RISC-V). And implementing this ARM instruction makes the core more complicated with little benefit. As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment. The real weak points of RISC-V are: - no trap on integer overflow and invalid FP results . Overflows cause vulnerabilities - no optimizations for fast context switch, which is required for dumping legacy unsafe monolithic kernels, especially in age of AI actively searching for vulns - weird vector extensions