You're right. I just tested it in Xilinx ISE 13.4 and it seemed to work without using any assign as both a single wire and a bus. I just recall seeing an error

You're right. I just tested it in Xilinx ISE 13.4 and it seemed to work without using any assign as both a single wire and a bus. I just recall seeing an error message at some point in the past which was about something similar.