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> Designing a good 64-bit ISA [...] is easy [...] could design such an ISA in a couple of weeks Let me know when you've got it all worked out and published. Sh
by indrora 2mo ago
> Designing a good 64-bit ISA [...] is easy [...] could design such an ISA in a couple of weeks
Let me know when you've got it all worked out and published. Should be easy, right?
- exmadscientist 2mo agoIt is the easy part. Four weeks is plenty of time. That's why it's so bizarre that the RISC-V design is so awful. The hard part is the software support side (though, as comments elsewhere in the thread point out, AI is pretty helpful there) and then those lovely pieces like specifying the precise behavior of interrupts. If it had a snowball's chance in hell of going in to any kind of production anywhere, I'd have no problem spending the next month laying out an ISA. But, again, as this thread makes very, very clear: ISA really just doesn't matter.
- phire 2mo ago> That's why it's so bizarre that the RISC-V design is so awful. Not bizarre. The design is a direct result of the biases of its initial designers, and its original intended use-case. And TBH, if you assess it by its original design criteria, it's actually pretty good. It's just by the time RISC-V had escaped containment and was starting to become a general purpose open ISA, it was a little too late to start from the beginning and consider what the correct design criteria should even be.
- exmadscientist 2mo agoVery true... but I can't help but note that basically every person I've ever met with significant experience with multiple architectures at this level, and not connected in some way to RISC-V, utterly hates the thing. That feels like a "don't release yet" flag to me! But I hear you.
- pseudohadamard 2mo agoIt looks an awful lot like something that was designed by a sizeable committee made up mostly of academics, most of whom won't have written ten lines of code in as many years. I don't actually know in this case, but I've had to sit and watch standards created in this manner, and Dmitry's description of the RISC-V mess matches their output fairly closely, a chaotic mess that includes every idea everyone on the standards committee has ever had, all made optional so no-one will vote against it when it comes to balloting.
- snapplebobapple 2mo agoHow many people are working on this in your couple years example? Is that just one guy or a team of 20 or something else? Whats the average salary for the team *n this scenario?
- exmadscientist 2mo agoI said "me" and "four weeks" because laying out an ISA is a pretty straightforward job for one person in one month. The deliverable would be a (theoretically) complete specification PDF like RISC-V's. I have little doubt that I or Adrian could do it, or plenty of others. It might not reach the quality of something like AArch64 with that level of resources, but it's not hard to beat RISC-V.
- snapplebobapple 2mo agoI am trying to figure out if i can afford to make it happen or not lol. Would the labour coat of getting to something good with the support infra be a fewmillion or tens of millions?
- exmadscientist 2mo agoAre you trying to get to a working simulator, a working core in HDL/FPGA, a thoroughly debugged and validated core in HDL, a fast core in HDL, a validated fast core in HDL, or functioning silicon in hand? I'd guess low six figures for the beginning of that list and mid eight figures for the end. Real silicon also needs all the uncore stuff, which is easy if you don't care how it performs and very very hard if you do.