4 ms·
RISC-V is pretty unoptimisable though; the industry has had its fair share of pretty lackluster MIPS and MIPS-like clones in embedded, and they've been mainly h
by userbinator 2mo ago
RISC-V is pretty unoptimisable though; the industry has had its fair share of pretty lackluster MIPS and MIPS-like clones in embedded, and they've been mainly high-volume low-cost "cheap and good enough" SoCs. To be competitive with ARM and x86 you really need higher code density and better, more complex instructions.
- joha4270 2mo agoTo be competitive with ARM and x86 they need a talented design team creating fast and wide cores on a modern node. (which I expect to take a decade at least) For the vast majority of non-number-crunching code any theoretical difference between instruction sets vanishes in the noise of core design.
- ithkuil 2mo agoGenuine question: what makes ARM64 a denser ISA compared to RISC-V ?
- userbinator 2mo agoThey tried to squeeze all they could into 32 bits, which is why there are things like load/store pair, bitfield extracts, etc.
- akoboldfrying 2mo ago> RISC-V is pretty unoptimisable though Is it? So there's no scope for different levels of pipelining, out-of-order execution with various numbers of execution units, branch prediction of various levels of sophistication, L1 cache of various amounts, multiplication and division implemented in various ways from slow but low chip area and power consumption to fast with high chip area or power consumption? Because those are all things that have major performance impact even on plain "RISC-style" x86-64 code.
- camel-cdr 2mo agoRISC-V has higher code density than Arm and x86 and all three have a comparible uop density, but RISC-V has a slightly higher average instruction count. What more complex instructions are missing?