3 ms·
I took a quick look at the IEEE 1800-2009 LRM (SystemVerilog, a proper superset of Verilog), and I can't see any BNF production that allows this. I think this
by jgw 14y ago
I took a quick look at the IEEE 1800-2009 LRM (SystemVerilog, a proper superset of Verilog), and I can't see any BNF production that allows this. I think this is a case of iverilog being somewhat permissive.
In looking it up, I did come across the keyword "alias", which I was not familiar with, that effectively does what you've done here.
That said, it doesn't detract from an enjoyable tutorial. It's nice to see a little ASIC content on HN - duly upvoted!
- PieSquared 14y agoThanks! Nice to know. I must've picked the habit up before from just reading code on the internet (as per my other comment in this thread), but I'll try to phase this out. This is what I love about Hacker News - people commenting really know their stuff, almost always well enough to teach me something :)
- jgw 14y agoWell, apparently I don't know what I'm talking about at all - it does work in the 3 major simulators. Typo in my code. Ooops. It appears to be valid, and does not require "assign". This is what I like about HN - smart people keeping me on my toes!