For future reference (since I can't edit): I spent a while researching and couldn't find any definitive answer, but found some places which supported the implic

For future reference (since I can't edit): I spent a while researching and couldn't find any definitive answer, but found some places which supported the implicit assignment ([0], [1]). However, these aren't anything official, so I think ultimately it just depends on what your particular implementation supports... [0] http://www.verilogtutorial.info/chapter_2.htm http://www.verilogtutorial.info/chapter_2.htm [1] http://www.doulos.com/knowhow/verilog_designers_guide/wire_assignments/ http://www.doulos.com/knowhow/verilog_designers_guide/wire_a...