4 ms·
I'm not even sure inspection and quality control is done at the fab. At least with logic ICs, they either testing/QC/bining as part of packaging (before dicing
by phire 2mo ago
I'm not even sure inspection and quality control is done at the fab.
At least with logic ICs, they either testing/QC/bining as part of packaging (before dicing), or even have factories that specialise in just testing/QC/Binning. Such fallacies need to be flexible enough to deal with thousands of different IC designs, and there is no reason to tie them to a given process node.
I guess with memory, there are only three-ish designs (DDR, LPDDR, HBM), so maybe it does make sense to integrate testing/QC/binning into the fab.
But I doubt they would have any trouble switching it out.
- gaigalas 2mo ago> packaging (before dicing) packaging before dicing? That makes no sense.
- phire 2mo agoIMO, dicing counts as part of packaging. So before the dicing step of packaging.
- gaigalas 2mo agoEach die on the wafer is kind of different. Light is not all the same, usually dies on the center of the wafer are better and it gets worse as you move outside. That plays out in binning, and it involves even design (laying out dies on the wafer such as the imperfections produce still usable ones, perhaps with some stuff disabled or running on lower specs). So, there is some sort of QA at that point (seeing how bad the bad dies are), which also feeds into adjusting following batches. DDR5 is already more complicated at that step. As I mentioned, it has ECC on the die and all other sorts of complications. A clean reuse of a DDR4 process seems unfeasible. There's significant investment needed for DDR5 even for what you consider "dicing".