4 ms·
Bus cycles can be arbitrarily long on any processor that has memory cycles with a hand shake requiring an ack, with no timeout. E.g. we can build a board aroun
by kazinator 2mo ago
Bus cycles can be arbitrarily long on any processor that has memory cycles with a hand shake requiring an ack, with no timeout.
E.g. we can build a board around a MC68000 where we make it lock up forever in a bus cycle, waiting for a DTACK that doesn't arrive.
Some early microprocessors had clocked bus cycles without handshaking. They would put out an address on some address lines and signal some line together with a read/write indication, and then expect the transfer to be completed within some clock cycles. If nothing is attached to the address, they would read whatever values are on the bus, like maybe all 1's if it is an open drain system that requires the transmitting device to pull to ground to indicate zero.
I'd say that kind of thing belongs to a hall of shame; it requires software hacks to interface with anything that can't keep up with the prescribed bus cycle.
- Joel_Mckay 2mo agoIn general, more complex processors have latency issues, and in some ways modern chips have actually become worse with each design iteration. https://en.wikipedia.org/wiki/Metastability_(electronics) https://en.wikipedia.org/wiki/Metastability_(electronics) Ultimately... failure modes must arise because naive gate design simulation models can't determine issues in a computationally feasible time frame. The consequences of "fixing" CDC prone design flaws makes a processor many times slower (8 to 16 times slower on my dumb attempt), and develops weird alien design features very different from Von Neumann architectures. This is why we can't have nice things. =3
- kazinator 2mo agoI smell Buridan's ass. :)
- inigyou 2mo agoBus cycles can also be arbitrarily long on those microprocessors if they don't use dynamic logic - you can stop the clock.
- NooneAtAll3 2mo ago> Times are normalized based on the CPU base clock frequency
- nxobject 2mo ago> E.g. we can build a board around a MC68000 where we make it lock up forever in a bus cycle, waiting for a DTACK that doesn't arrive. IIRC, early 68k Macs had processor upgrades hooked onto the 68k bus and did exactly this - an early boot driver run by the “actual” CPU coordinated handoff with the expansion CPU’s bootstrap ROM.