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I am talking about reconfigurable gates to implement an LLM in silicon, i.e. an FPGA...
by harrouet 2mo ago
I am talking about reconfigurable gates to implement an LLM in silicon, i.e. an FPGA...
- xprnio 2mo agoWhat might the “parameters/layers to gates” ratio look like? My naive and uninformed guess would be that 1B+ parameter would also need a 1B+ gate FPGA, but according to google they typically range from tens of thousands to several million (which would still be a fraction of a billion).