4 ms·
Related: AXI SystemVerilog synthesizable FPGA IP modules and verification infrastructure for high-performance on-chip communication: https://github.com/pulp-p
by peter_d_sherman 3mo ago
Related:
AXI SystemVerilog synthesizable FPGA IP modules and verification infrastructure for high-performance on-chip communication:
https://github.com/pulp-platform/axi https://github.com/pulp-platform/axi
Verilog PCI express related FPGA components with PCIe to AXI and AXI lite bridges and a flexible, high-performance DMA subsystem:
https://github.com/alexforencich/verilog-pcie https://github.com/alexforencich/verilog-pcie