Hey, I made one of these too[1]. One of the cool things about my implementation is that the sample loop is carefully written in cycle counted assembly to sample

Hey, I made one of these too[1]. One of the cool things about my implementation is that the sample loop is carefully written in cycle counted assembly to sample the ADC of the teensy 2.0 at the absolute maximum frequency. I like your blogpost a lot more than mine though. [1] Github: https://github.com/DelusionalLogic/Frametime https://github.com/DelusionalLogic/Frametime, Blogpost: https://www.jnsn.dev/posts/frametime/ https://www.jnsn.dev/posts/frametime/, and followup: https://www.jnsn.dev/posts/fastisslow/ https://www.jnsn.dev/posts/fastisslow/