3 ms·

My point is that fixed-length instructions are supposed to be easier to decode than variable-length ones, right? If not, then why even bother with fitting imme

My point is that fixed-length instructions are supposed to be easier to decode than variable-length ones, right? If not, then why even bother with fitting immediates and inventing LUI/AUIPC, just have a 48-bit long LI instruction. The same goes for 64-bit, an 80-bit LI.W is still shorter than the piecemeal construction with several instructions. If yes, then the small cores are arbitrarily given a burden of supporting variable-length instructions, supposedly efficiently: if your instruction fetch is 16-bit wide, you need two fetches to fetch a single 32-bit instruction, which sucks; if it's 32-bit wide, you need to conditionally stash the upper half for the next fetch cycle, and still prefetch yet more 32-bits because that upper half may contain only a half of a full 32-bit instruction; alternatively, you can fetch 32-bits at alternated aligned/misaligned addresses and ignore the inefficiency of throwing away re-fetched bits — again, all of this sucks.

rwmj 3mo ago
Yes, fixed-length instructions are easier to decode, but that also means a hard upper limit on the number of instructions that could ever be supported. Which is obviously a problem for a future-proof architecture. The rationale for this and also for confining the base set to 32 bit is explained here: https://docs.riscv.org/reference/isa/v20250508/unpriv/extending.html#35-2-risc-v-extension-design-philosophy https://docs.riscv.org/reference/isa/v20250508/unpriv/extend...
- Joker_vD 3mo ago
  I've read that rationale, and it's, well, I'm not going to say it's lying, but it's insincere. By the time it was written, they already settled on 16-bit alignment, and fetching (and then decoding) 16-bit aligned 32-bit instructions is either inefficient, or hard, or requires extra circuitry (or an instruction cache).
  - rwmj 3mo ago
    High performance RISC-V chips exist from Rivos, Ventana and others, and high performance variable length chips also exist in general (AMD, Intel). So in actual reality it increases complexity somewhat, but is not a problem.
    - Joker_vD 3mo ago
      sighs This kind of discussion is so annoying... I start with "RISC-V's decision to make 32-bit instructions only 16-bit aligned complicates instruction fetch and decoding", and the response is "For high performance RISC-V implementations, it's a trivial matter" (which is true), I response with "But then why even bother with mostly-fixed-but-not-quite instruction length, just make a properly variable length ISA, it'd even simplify the instructions", and the reply is "the low-end implementations would struggle with decoding that efficiently" — but they already struggle with instruction fetch when they implement C extension! Nah, it's fine, the high-end chips can cope with that. And round and around this discussion goes... Apparently, RISC-V has no downsides at any end of the price spectrum, what a marvelous ISA.
      - rwmj 3mo ago
        If you have some specific question I may be able to answer it, since I've been involved with RISC-V for over a decade, dealt with all the main companies involved, written papers, etc. but so far I see no actual question or concrete objection.
- dmitrygr 3mo ago
  [flagged]
  - camel-cdr 3mo ago
    You can see the encoding limitation it in the design on SVE, which only has destructive operations, but MOVPRFX, which is a round about way of doing 64-bit instructions, without doing 64-bit instructions.
    - dmitrygr 3mo ago
      When the top perf per watt or perf per MHz machine is RISCV, we'll talk. Until then, lol.
      - brucehoult 3mo ago
        Self-evidently, you therefore won't be the person building this machine.
        dmitrygr 3mo ago
        Nope. I don’t want to work on systems that self-handicap in dumb and predictable ways. Mistakes happen. But mistakes that were preventable and knowable at design time … they are inexcusable, and RISCV is chock-full of those.
        brucehoult 3mo ago
        I disagree.
      - sylware 3mo ago
        Many here wish for the non IP-locked RISC-V to get performant micro-achitectures for embedded/server/desktop/mobile that on the latest silicon process (without that, you can have a very good micro-architecture, that won't probably make the difference). If some RISC-V high performance CPU manufacturers are being bought by big hardware actors: either they are scared of its competition and want to scrap it or they want to be part of RISC-V.
brucehoult 3mo ago
> small cores are arbitrarily given a burden of supporting variable-length instructions Even the smallest commercial microcontroller cores e.g. the CH32V003, support the C extension. They strip out other things, such as half the integer registers, but they keep C. And that's in a market where you can use literally any combination of extensions you want, because the customers compile all their own code, and you just tell them what ISA string to use.

rwmj 3mo ago

Yes, fixed-length instructions are easier to decode, but that also means a hard upper limit on the number of instructions that could ever be supported. Which is obviously a problem for a future-proof architecture. The rationale for this and also for confining the base set to 32 bit is explained here: https://docs.riscv.org/reference/isa/v20250508/unpriv/extending.html#35-2-risc-v-extension-design-philosophy https://docs.riscv.org/reference/isa/v20250508/unpriv/extend...

Joker_vD 3mo ago
I've read that rationale, and it's, well, I'm not going to say it's lying, but it's insincere. By the time it was written, they already settled on 16-bit alignment, and fetching (and then decoding) 16-bit aligned 32-bit instructions is either inefficient, or hard, or requires extra circuitry (or an instruction cache).
- rwmj 3mo ago
  High performance RISC-V chips exist from Rivos, Ventana and others, and high performance variable length chips also exist in general (AMD, Intel). So in actual reality it increases complexity somewhat, but is not a problem.
  - Joker_vD 3mo ago
    sighs This kind of discussion is so annoying... I start with "RISC-V's decision to make 32-bit instructions only 16-bit aligned complicates instruction fetch and decoding", and the response is "For high performance RISC-V implementations, it's a trivial matter" (which is true), I response with "But then why even bother with mostly-fixed-but-not-quite instruction length, just make a properly variable length ISA, it'd even simplify the instructions", and the reply is "the low-end implementations would struggle with decoding that efficiently" — but they already struggle with instruction fetch when they implement C extension! Nah, it's fine, the high-end chips can cope with that. And round and around this discussion goes... Apparently, RISC-V has no downsides at any end of the price spectrum, what a marvelous ISA.
    - rwmj 3mo ago
      If you have some specific question I may be able to answer it, since I've been involved with RISC-V for over a decade, dealt with all the main companies involved, written papers, etc. but so far I see no actual question or concrete objection.
dmitrygr 3mo ago
[flagged]
- camel-cdr 3mo ago
  You can see the encoding limitation it in the design on SVE, which only has destructive operations, but MOVPRFX, which is a round about way of doing 64-bit instructions, without doing 64-bit instructions.
  - dmitrygr 3mo ago
    When the top perf per watt or perf per MHz machine is RISCV, we'll talk. Until then, lol.
    - brucehoult 3mo ago
      Self-evidently, you therefore won't be the person building this machine.
      - dmitrygr 3mo ago
        Nope. I don’t want to work on systems that self-handicap in dumb and predictable ways. Mistakes happen. But mistakes that were preventable and knowable at design time … they are inexcusable, and RISCV is chock-full of those.
        brucehoult 3mo ago
        I disagree.
    - sylware 3mo ago
      Many here wish for the non IP-locked RISC-V to get performant micro-achitectures for embedded/server/desktop/mobile that on the latest silicon process (without that, you can have a very good micro-architecture, that won't probably make the difference). If some RISC-V high performance CPU manufacturers are being bought by big hardware actors: either they are scared of its competition and want to scrap it or they want to be part of RISC-V.

brucehoult 3mo ago

> small cores are arbitrarily given a burden of supporting variable-length instructions Even the smallest commercial microcontroller cores e.g. the CH32V003, support the C extension. They strip out other things, such as half the integer registers, but they keep C. And that's in a market where you can use literally any combination of extensions you want, because the customers compile all their own code, and you just tell them what ISA string to use.