4 ms·
As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere betwe
by adrian_b 4mo ago
As it can be seen from the photos, horizontally the features are much bigger than 5 nm.
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.
The supposed node size refers to horizontal dimensions, not to vertical dimensions.
Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.
The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.
However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.
- gabrielhidasy 4mo agoJust get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.
- kailden 4mo agoExactly. WatsonX AI quantum angstroms for e-business.
- xattt 4mo agoNow with Tivoli Monitoring!
- quantum_state 4mo agoAt some point, people would not know if they have the deal or not have the deal in this new era of quantum e-business ...
- scythe 4mo agoThe scale bar on the far right "photo" (micrograph?) doesn't make sense. It is only slightly less than half the scale bar on the middle photo (10 nm), but the image is clearly scaled up by much more than 2x. Individual silicon atoms are circled in the right photo, but the covalent radius of silicon is about 0.11 nm, so they should be much smaller if the scale bar is accurate.
- wongarsu 4mo agoThe scale bar also got about 50% longer, which would imply a 3x zoom. That also seems about right based on the relative feature sizes. Same thing happened between the first and second image.
- meindnoch 4mo ago>The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer We should flip the transistors sideways then!
- MengerSponge 4mo agoShades of "You can't go to the sun! You'll burn alive!" "Duh! That's why we're going at night!"
- sylware 4mo agoMarketing scams has been the norm for the silicon industry for a big decade. How would you fix that? This is a global scam. Big Markets regulating them: that would have to be the USA and EU.