3 ms·
My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through st
by pseudosavant 4mo ago
My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?
- makeitdouble 4mo agoIf they're adding a dimension, the marketing should reflect that. I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
- y1n0 4mo ago“TeraThread”
- ncruces 3mo agoShould population density in cities also be measured in hab/km³ rather than hab/km²? We are used to stacking people vertically in cities.
- makeitdouble 3mo agoReally good point. There's a world of difference between being vertically spaced and packed on a single floor.
- shash 3mo agoCorrection: it’s not stacking. They do things like FinFET (turning the gates in the third dimension) and gate-all-around which increases the density of transistors per unit area. But they don’t have layers of transistors. At least in the logic and analog processes.