13 ms·
The memory pipeline just starts one cycle later than now. Effective address is calculated during the first cycle of the instruction. The microcode then waits fo
by nand2mario 3mo ago
The memory pipeline just starts one cycle later than now. Effective address is calculated during the first cycle of the instruction. The microcode then waits for it to finish with the DLY (delay) micro-op, which releases one cycle later.
- JdeBP 3mo agoSo cycle insertion. I presume that the DLY was synthetic, and was not explicitly added to the microcode ROM.