3 ms·
Within an IC you don't have large obstructions for metal layers, distances are short, and buffers can be inserted at will to manage SI.
by kevin_thibedeau 5mo ago
Within an IC you don't have large obstructions for metal layers, distances are short, and buffers can be inserted at will to manage SI.
- pjc50 5mo agoIt has been about 20 years since I worked on this (clock gating and clock buffering), but .. > distances are short I remember we had a catastrophic error for "wire longer than 2cm". > and buffers can be inserted at will to manage SI. Effective buffering of large nets was a massive pain. Areas where you want to buffer are inevitably areas with a very high level of placement congestion. So you push some cells out of the way to add a buffer. That ends up worsening their timing. So they need a bit more sizing/buffering. Rinse and repeat for a few hours. ( https://web.archive.org/web/20071028033035/http://www.edn.com/article/CA601818.html https://web.archive.org/web/20071028033035/http://www.edn.co... ; long since absorbed into Cadence)