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1.2TB/s memory bandwidth from a CPU. Oh boy. What the fuck is Intel doing all this time and can’t deliver equivalent performance?
by elorant 5mo ago
1.2TB/s memory bandwidth from a CPU. Oh boy. What the fuck is Intel doing all this time and can’t deliver equivalent performance?
- baal80spam 5mo ago> What the fuck is Intel doing all this time The thing is, it doesn't have to do anything. It is busy getting bailed out, I guess.
- PaulKeeble 5mo agoIf you don't have to worry about replaceable sticks and users choosing their own memory manufacturer, speed and size then you can shorten the traces and improve connectivity including the bus width and its latency. I can't help but think the DIMM format is coming to an end.
- elorant 5mo agoI don't expect them to change their entire pipeline. But surely they could offer a unified RAM lineup that caters to specific needs. Not everyone needs that fast RAM access but for those who do it could be nice to have an option. The writing is on the wall for years now.
- pizza234 5mo ago> Not everyone needs that fast RAM access but for those who do it could be nice to have an option. The writing is on the wall for years now. There is an option already, at least from AMD, in the HEDT segment - Threadripper/Pro has 4/8 channels (although the bandwidth is not a high as Apple chips).
- justincormack 5mo agoThis is exactly what Apple has done, but it does mean soldered memory, as socketed memory at these speeds still hasn't happened. In the server market that is pretty unpopular (even the hyperscalars are apparently reusing DDR4 with CXL in newer machines). DDR6 apparently has twice the memory bandwidth of DDR5 so that will bring it back in line, to around 1TB/s for 12 channels, so comparable but still with standard memory sticks.
- 15155 5mo agohttps://en.wikipedia.org/wiki/CAMM_(memory_module) https://en.wikipedia.org/wiki/CAMM_(memory_module)
- cduzz 5mo agoHigh Bandwidth Memory uses thousands of interconnects for the data bus. DDR style memory typically uses in the neighborhood of 64 bit transfers at a time. HBM tends to be integrated onto the package (board, multi chip module, die) because there are really tight signaling and wire routing constraints that make "modularity" impossible. I remember back in the day you could get motherboards for your 286, 386, and sometimes even 486 with external L1 / L2 / L3 cache -- you'd buy a bunch of static ram dips that you'd populate sockets next to the CPU, and set a bios or DIP switch to enable it. These days that's just not practical because there are too many wires interconnecting the cache to the dies and cache coherence logic, and the speed of light is just too slow and electricity is too messy to put "external" to the die/chip/package, even if the packaging issues could be addressed. HBM memory is similar -- it's not practical to make a generic interconnect that'd actually work reliably enough to provide field replaceable memory modules as you can with DDR style dimms. EDIT: Apparently I'm totally wrong in that these "SOCAMM2" modules have thousands of pads (like a CPU socket) and can in fact run with the same data bus width (1024 bits wide!) as "local" HBM. Very cool. And please ignore my out of date blatherings above. It's still not quite as fast as if you put the HBM in the package, but it's way faster than the DDR style setup.
- rasz 5mo agoApple doesnt use HMB, but its marketing successfully convinced people it does ant thats why ram has to be soldered.
- veber-alex 5mo agoVera doesn't use soldered memory, it uses SOCAMM2.
- elorant 5mo agoMac ultras would be great if they offered pcie slots to put nvme drives on and ideally an infiniband network card.
- mimd 5mo agoNew to the field? Intel did xeon max in the last gen, with 64GB HBM 2e, 1.6TB/s per 56 cores. It was not a great success.