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How does it compare to something like VexRisc [0] with respect to its capabilities? I know having x86 support is a metric all by itself. [0] https://github.co
by mycall 5mo ago
How does it compare to something like VexRisc [0] with respect to its capabilities? I know having x86 support is a metric all by itself.
[0] https://github.com/spinalhdl/vexriscv https://github.com/spinalhdl/vexriscv
- phire 5mo agoNo contest really: RISCV is a much better ISA, VexRISC is a hyper-optimised implementation of it (for FPGAs), and it's not hindered by trying to be microcode compatible. The roughly equivalent VexRISC configuration (full with MMU) is only 2736 LUTs, running at 124 Mhz (on Cyclone V, which I'm pretty sure is the same arch)
- UncleOxidant 5mo agoA lot of RISCV implementations are going to be better and take a lot less resources in an FPGA due to the much more-easily-decoded ISA. What I was saying above was that I was surprised that they could get an x86 into that few LUTs as the x86 ISA is not well suited to efficient implementations.