3 ms·

Author here if anyone has questions...

• monocasa 5mo ago
  When you say that the 125 added memory management, what does that mean a little more specifically? My guess is either PDP-11/z280 style paging without page tables (the 16 bit address space makes just having enough IO registers to cover the address space tractable) or some simple segmentation hardware, but it'd be neat if there was another hardware object capability system I didn't know about.
  • kens 5mo ago
    The Mitra 125 had memory segmentation. It seems similar to the 8086, with descriptors that specified base address and length for a segment. Accessing memory outside a segment caused a trap.
    • atq2119 5mo ago
      That sounds more like the 80286/80386.
      • kens 5mo ago
        You're right; I should have said x86-style.
• skissane 5mo ago
  Do we know anything about the software that ran on it? What language it was developed on, what host platform was used for development, etc? Does any of the code survive?
  • kens 5mo ago
    Much of the software was in a language called HAL/S (High-order Assembly Language/Shuttle), using an IBM 360/370 for compilation. Other software was written in Fortran. See https://www.cs.toronto.edu/XPL/hal.html https://www.cs.toronto.edu/XPL/hal.html and https://repository.arizona.edu/bitstream/handle/10150/613923/ITC_1979_79-09-4.pdf https://repository.arizona.edu/bitstream/handle/10150/613923...
    • skissane 5mo ago
      Interesting... I know about HAL/S being used for the AP-101S Shuttle software, inter alia. I didn't realise it was used for the CII Mitra 125 as well. I would have assumed the Europeans would have used something else.
• tasty_freeze 5mo ago
  What frequency did it it cycle at? Any idea how many instructions per second it could process?
  • kens 5mo ago
    I don't know what the clock speed was, but it performed about 525,000 addition instructions per second. (1.9µs addition time)