4 ms·
looks like there's no mention of soft-floats support, like in Hazard3 cores see f.e.: https://wren.wtf/shower-thoughts/marks-magic-multiply/ https://wren.wtf/s
by NooneAtAll3 5mo ago
looks like there's no mention of soft-floats support, like in Hazard3 cores
see f.e.: https://wren.wtf/shower-thoughts/marks-magic-multiply/ https://wren.wtf/shower-thoughts/marks-magic-multiply/
- Narishma 5mo agoBecause that's not a RISC-V standard but a custom extension implemented by one chip.