…except this Zync FPGAs, it has a processors in it. I've never understood why the Zync CPU has to communicate with the rest of the FPGA over external busses.

…except this Zync FPGAs, it has a processors in it. I've never understood why the Zync CPU has to communicate with the rest of the FPGA over external busses. Why not connect a set of latches or LUTs to the instruction decoder and data bus, so you can create custom instructions?