4 ms·
Isn't part of that due to Rosetta relying on Apple extensions to ARM to mimic x86-64 memory semantics?
by whizzter 5mo ago
Isn't part of that due to Rosetta relying on Apple extensions to ARM to mimic x86-64 memory semantics?
- MrBuddyCasino 5mo agoThe x86 memory model (TSO) is not Apple‘s invention, its a standard ARM extension.
- m132 5mo agoThe memory model by itself isn't, however Apple implemented it before Arm released an (incompatible) set of extensions that approach the problem at the instruction level instead of adding an Apple-style global TSO on/off switch in an IMPDEF register [0]. [0] https://lkml.org/lkml/2024/4/10/1531 https://lkml.org/lkml/2024/4/10/1531
- MrBuddyCasino 5mo agoI stand corrected!
- drob518 5mo agoI thought Apple Silicon also has some extra hardware support for handling x86 flags emulation for Rosetta. But perhaps I’m remembering that incorrectly.