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ESP32-S3 may be the worse model to run Rust on due to the XTensa cores that makes the toolchain unnecessarily complicated. The newer model, C3, C6, C5 all have

ESP32-S3 may be the worse model to run Rust on due to the XTensa cores that makes the toolchain unnecessarily complicated. The newer model, C3, C6, C5 all have RSIC-V cores which make it a dream to run Rust (basically: rustup target add riscv32imac-unknown-none-elf). Here is a good introduction: https://kerkour.com/introduction-to-embedded-development-with-rust https://kerkour.com/introduction-to-embedded-development-wit...

topspin 5mo ago
> ESP32-S3 may be the worse model to run Rust on due to the XTensa cores that makes the toolchain unnecessarily complicated. Indeed. ESP32-S31 appears to target exactly this concern in the popular "S3" segment. It's basically a updated S3, with faster and newer wireless and memory, and it adopts a pair of RISC-V cores in place of the Xtensa cores.
- sowbug 5mo ago
  My brain broke a little when I read this. Today I learned the C stands for Core, and the S stands for Speed, or Strength, or maybe Superior. My working assumption that C meant RISC-V and S meant Xtensa was incorrect.
  - topspin 5mo ago
    That's a widely shared misunderstanding. The letters are market segments. The "S" segment is really popular. Despite the introduction of many Espressif RISC-V devices, one still sees lots of Xtensa S3 stuff. An excellent example is Unexpected Maker's line of ESP32-S3 boards. ESP32-S31 is going to be a big hit, and RISC-V is only part of that. More GPIO are very welcome. The CLIC (core local interrupt control) is another subtle win that is lost in mainstream headlines: it provides Cortex NVIC level of interrupt management, enabling awesome things like RTIC work without compromise. I imagine using one of these with core 0 running plain old FreeRTOS handing Wi-Fi/OTA/etc., and core 1 exclusively running a Rust RTIC/SRP application, nailing real time peripheral activity. The only miss is the lack of 5GHz. Nothing is perfect, and that's not a deal killer in most cases.
    - MrBuddyCasino 5mo ago
      Also, finally bt audio classic and ble audio in one chip!

topspin 5mo ago

> ESP32-S3 may be the worse model to run Rust on due to the XTensa cores that makes the toolchain unnecessarily complicated. Indeed. ESP32-S31 appears to target exactly this concern in the popular "S3" segment. It's basically a updated S3, with faster and newer wireless and memory, and it adopts a pair of RISC-V cores in place of the Xtensa cores.

sowbug 5mo ago
My brain broke a little when I read this. Today I learned the C stands for Core, and the S stands for Speed, or Strength, or maybe Superior. My working assumption that C meant RISC-V and S meant Xtensa was incorrect.
- topspin 5mo ago
  That's a widely shared misunderstanding. The letters are market segments. The "S" segment is really popular. Despite the introduction of many Espressif RISC-V devices, one still sees lots of Xtensa S3 stuff. An excellent example is Unexpected Maker's line of ESP32-S3 boards. ESP32-S31 is going to be a big hit, and RISC-V is only part of that. More GPIO are very welcome. The CLIC (core local interrupt control) is another subtle win that is lost in mainstream headlines: it provides Cortex NVIC level of interrupt management, enabling awesome things like RTIC work without compromise. I imagine using one of these with core 0 running plain old FreeRTOS handing Wi-Fi/OTA/etc., and core 1 exclusively running a Rust RTIC/SRP application, nailing real time peripheral activity. The only miss is the lack of 5GHz. Nothing is perfect, and that's not a deal killer in most cases.
  - MrBuddyCasino 5mo ago
    Also, finally bt audio classic and ble audio in one chip!