3 ms·
Does anyone know why the jal RISC-V instruction scrambles it bits in this way? https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#jal https://msyksph
by aftbit 6mo ago
Does anyone know why the jal RISC-V instruction scrambles it bits in this way?
https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#jal https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html...
- soxfox42 6mo agoRISC-V's instruction encoding is designed to keep the bits of literals in common positions between different instruction types. I believe this is to simplify/speed up instruction decoding. The MSB of the literal is always the MSB of the instruction, which makes sign extension consistent. Most of the other bits in the J-type encoding line up nicely with the I-type or U-type encodings.