4 ms·

It'd be a neat trick to have a single unified language which could bridge the gap between software and hardware description languages.

lioeters 6mo ago
It's an intriguing idea. Having experience with software but almost none (only hobbyist) in hardware, I imagine it'd require a strong type system and mathematical foundation. Perhaps something like Agda, a language that is a proof assistant and theorem prover, with which one can write executable programs. https://en.wikipedia.org/wiki/Agda_(programming_language) https://en.wikipedia.org/wiki/Agda_(programming_language)
- timschmidt 6mo ago
  I wonder if an escape hatch like Rust's unsafe{} would be enough... a hardware{}. The real complexity likely lies in how to integrate the synthesis tools with the compiler and debugger. The timing model. A memory model like Rust's would certainly aid in assuring predictable behavior, but I'm not certain it would be sufficient.
adrian_b 6mo ago
The hardware description languages, even if they have a single language specification, are divided into 2 distinct subsets, one used for synthesis, i.e. for hardware design, and one used for simulation, i.e. for hardware verification. The subset required for hardware synthesis/design, cannot be unified completely with a programming language, because it needs a different semantics, though the syntax can be made somewhat similar, as with VHDL that was derived from Ada, while Verilog was derived from C. However, the subset used for simulation/verification, outside the proper hardware blocks, can be pretty much identical with a programming language. So in principle one could have a pair of harmonized languages, one a more or less typical programming language used for verification and a dedicated hardware description language used only for synthesis. The current state is not too far from this, because many simulators have interfaces between HDLs and some programming languages, so you can do much verification work in something like C++, instead of SystemVerilog or VHDL. For instance, using C++ for all verification tasks is possible when using Verilator to simulate the hardware blocks. I am not aware of any simulator that would allow synthesis in VHDL coupled with writing test benches in Ada, which are a better fit than VHDL with C++, but it could be done.
- OneWingedShark 6mo ago
  I read about a VHDL that used DIANA. DIANA was an IR in some Ada compilers; I would imagine that such a common IR would facilitate exactly those test benches with an ease that borders on 'ludicrous'.
- a96 6mo ago
  I remembered being vaguely amused learning VHDL how familiar it felt because I'd learned some Ada long ago. But yes, it's not a deep connection. I don't know if there would be much to be gained from bringing them together.
synack 6mo ago
I’ve written some bit-banged serial drivers in Ada. It’s not exactly VHDL, but it rhymes. https://github.com/JeremyGrosser/softdev/tree/master/src https://github.com/JeremyGrosser/softdev/tree/master/src

lioeters 6mo ago

It's an intriguing idea. Having experience with software but almost none (only hobbyist) in hardware, I imagine it'd require a strong type system and mathematical foundation. Perhaps something like Agda, a language that is a proof assistant and theorem prover, with which one can write executable programs. https://en.wikipedia.org/wiki/Agda_(programming_language) https://en.wikipedia.org/wiki/Agda_(programming_language)

timschmidt 6mo ago
I wonder if an escape hatch like Rust's unsafe{} would be enough... a hardware{}. The real complexity likely lies in how to integrate the synthesis tools with the compiler and debugger. The timing model. A memory model like Rust's would certainly aid in assuring predictable behavior, but I'm not certain it would be sufficient.

adrian_b 6mo ago

The hardware description languages, even if they have a single language specification, are divided into 2 distinct subsets, one used for synthesis, i.e. for hardware design, and one used for simulation, i.e. for hardware verification. The subset required for hardware synthesis/design, cannot be unified completely with a programming language, because it needs a different semantics, though the syntax can be made somewhat similar, as with VHDL that was derived from Ada, while Verilog was derived from C. However, the subset used for simulation/verification, outside the proper hardware blocks, can be pretty much identical with a programming language. So in principle one could have a pair of harmonized languages, one a more or less typical programming language used for verification and a dedicated hardware description language used only for synthesis. The current state is not too far from this, because many simulators have interfaces between HDLs and some programming languages, so you can do much verification work in something like C++, instead of SystemVerilog or VHDL. For instance, using C++ for all verification tasks is possible when using Verilator to simulate the hardware blocks. I am not aware of any simulator that would allow synthesis in VHDL coupled with writing test benches in Ada, which are a better fit than VHDL with C++, but it could be done.

OneWingedShark 6mo ago
I read about a VHDL that used DIANA. DIANA was an IR in some Ada compilers; I would imagine that such a common IR would facilitate exactly those test benches with an ease that borders on 'ludicrous'.
a96 6mo ago
I remembered being vaguely amused learning VHDL how familiar it felt because I'd learned some Ada long ago. But yes, it's not a deep connection. I don't know if there would be much to be gained from bringing them together.

synack 6mo ago

I’ve written some bit-banged serial drivers in Ada. It’s not exactly VHDL, but it rhymes. https://github.com/JeremyGrosser/softdev/tree/master/src https://github.com/JeremyGrosser/softdev/tree/master/src