3 ms·
Yeah exactly, and it’s absolutely dwarfed by the tail latency of going to DRAM in the first place. A cache miss is a 100x tail event vs. an L1 hit. The refresh
by foltik 6mo ago
Yeah exactly, and it’s absolutely dwarfed by the tail latency of going to DRAM in the first place. A cache miss is a 100x tail event vs. an L1 hit. The refresh stall is a further 5x on top of that, which barely registers if you’re already eating the DRAM cost.
- ufocia 6mo agoIt could be useful for large data set lookups where you're still limited to largely commodity hardware. Not sure how ~2-8x hardware costs needed to implement this reasonably would compare with costs of specialized hardware.