28 ms·
> RISC-V is little These days it's bi, actually :) Although I don't see any CPU designer actually implementing that feature, except maybe MIPS (who have stoppe
by hmry 6mo ago
> RISC-V is little
These days it's bi, actually :) Although I don't see any CPU designer actually implementing that feature, except maybe MIPS (who have stopped working on their own ISA, and now want all their locked-in customers to switch to RISC-V without worrying about endianness bugs)
- drob518 6mo agoWell, sort of. Instruction fetch is always little-endian but data load/store can be flipped into big. But IIRC the standard profiles specify little, so it's pretty much always going to be little. But yea, technically speaking data load/store could be big. Maybe that's important for some embedded environments.
- hmry 6mo ago> Well, sort of. Instruction fetch is always little-endian but data load/store can be flipped into big ARM works the same way. And SPARC is the opposite, instructions are always big-endian, but data can be switched to little-endian.