3 ms·

https://en.wikipedia.org/wiki/Power_ISA https://en.wikipedia.org/wiki/Power_ISA

ricardobeat 6mo ago
RISC-V is also open. That “some reason” is likely to be power/performance levels being quite far from ARM & Intel for consumer devices.
- vrganj 6mo ago
  China is building out RISC-V, just like they are leading actually-open AI. https://www.scmp.com/tech/big-tech/article/3347684/alibaba-debuts-its-latest-risc-v-based-chip-amid-shift-ai-agents https://www.scmp.com/tech/big-tech/article/3347684/alibaba-d... Weirdly, the authoritarian state is the one saving us from our own digital authoritarians.
  - NitpickLawyer 6mo ago
    > they are leading actually-open AI. How are they leading? If I parse this correctly, "actually" open would mean fully open data training and weights? Then, by this definition, I'm only aware of Olmo (AllenAI - Seattle), Apertus (Swiss) and to some degree (unclear what data was actually published) Nemotron (Nvda, US). What are some examples of chinese similar models? (I'm not aware of any).
- badgersnake 6mo ago
  RISC-V is slow though
  - snvzz 6mo ago
    RISC-V is an ISA. There's nothing inherently slow about it, anymore than there is anything inherently slow about x86 or ARM. High performance microarchitecture implementations are definitely possible. Some of them are available for licensing. At least one of them (Tenstorrent Ascalon) has been tapped out into a chip and will show up in development boards later this year.
    - badgersnake 6mo ago
      If you can’t buy a fast one, then it’s slow. It might not be slow forever, but it’s slow now. I’d love to see an open ISA that is fast. But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land.
      - snvzz 6mo ago
        >If you can’t buy a fast one, then it’s slow. Shrug. The first RVA23-compliant chips are coming soon. spacemiT K3 imminent (likely shipping boards this month) and Tenstorrent Ascalon (via Atlantis SoC devboard) this summer. These won't be the fastest CPUs available, but they'll meet the "fast enough" criteria for many uses and users. Multiple parties including Tenstorrent expect performance parity with the ARM and x86 offerings available at the same time by 2028. Note performance is mainly gated by access to latest fab nodes, which comes with costs that necessitate serious volume. They expect to be there by then. >But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land. The rationale was documented in the "Instruction Sets Should Be Free: The Case For RISC-V" paper[0]. Note OpenPOWER is mentioned but is not in the comparison. The reason for that is simple: RISC-V predates OpenPOWER. It was an obvious reaction to RISC-V, and they were too late, as RISC-V already had the industry's attention. Furthermore, Open is a lie; payment to IBM is required in practice. 0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...

RISC-V is also open. That “some reason” is likely to be power/performance levels being quite far from ARM & Intel for consumer devices.

vrganj 6mo ago
China is building out RISC-V, just like they are leading actually-open AI. https://www.scmp.com/tech/big-tech/article/3347684/alibaba-debuts-its-latest-risc-v-based-chip-amid-shift-ai-agents https://www.scmp.com/tech/big-tech/article/3347684/alibaba-d... Weirdly, the authoritarian state is the one saving us from our own digital authoritarians.
- NitpickLawyer 6mo ago
  > they are leading actually-open AI. How are they leading? If I parse this correctly, "actually" open would mean fully open data training and weights? Then, by this definition, I'm only aware of Olmo (AllenAI - Seattle), Apertus (Swiss) and to some degree (unclear what data was actually published) Nemotron (Nvda, US). What are some examples of chinese similar models? (I'm not aware of any).
badgersnake 6mo ago
RISC-V is slow though
- snvzz 6mo ago
  RISC-V is an ISA. There's nothing inherently slow about it, anymore than there is anything inherently slow about x86 or ARM. High performance microarchitecture implementations are definitely possible. Some of them are available for licensing. At least one of them (Tenstorrent Ascalon) has been tapped out into a chip and will show up in development boards later this year.
  - badgersnake 6mo ago
    If you can’t buy a fast one, then it’s slow. It might not be slow forever, but it’s slow now. I’d love to see an open ISA that is fast. But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land.
    - snvzz 6mo ago
      >If you can’t buy a fast one, then it’s slow. Shrug. The first RVA23-compliant chips are coming soon. spacemiT K3 imminent (likely shipping boards this month) and Tenstorrent Ascalon (via Atlantis SoC devboard) this summer. These won't be the fastest CPUs available, but they'll meet the "fast enough" criteria for many uses and users. Multiple parties including Tenstorrent expect performance parity with the ARM and x86 offerings available at the same time by 2028. Note performance is mainly gated by access to latest fab nodes, which comes with costs that necessitate serious volume. They expect to be there by then. >But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land. The rationale was documented in the "Instruction Sets Should Be Free: The Case For RISC-V" paper[0]. Note OpenPOWER is mentioned but is not in the comparison. The reason for that is simple: RISC-V predates OpenPOWER. It was an obvious reaction to RISC-V, and they were too late, as RISC-V already had the industry's attention. Furthermore, Open is a lie; payment to IBM is required in practice. 0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...