3 ms·
AFAIK, creating latches is just as easy in Verilog as in VHDL. They use the same model to determine when to create one. But with a solid design flow (which sho
by tverbeure 7mo ago
AFAIK, creating latches is just as easy in Verilog as in VHDL. They use the same model to determine when to create one.
But with a solid design flow (which should include linting tools like Spyglass for both VHDL and Verilog), it’s not a major concern.
- nickelpro 7mo agoSystemVerilog basically fixes this with always_comb vs always_latch. There's no major implementation which doesn't handle warning or even failing the flow on accidental latch logic inside an always_comb.